In the previous tutorials, boolean functions, boolean expressions, minimization of boolean expressions and implementation of a boolean function into logic gate diagram was discussed. It is possible to minimize a boolean function with less number of boolean variables and implement a logic gate diagram for it manually. But as the number of variables in a boolean function increases, not only its minimization becomes complex, designing a logic gate implementation for it also becomes cumbersome. In such case, computer based design tools are the ultimate resort.
这些数字电路设计工具使用硬件说明语言来描述,原型和测试数字电路。硬件说明语言是一种编程语言,它以文本形式描述了数字电路的硬件体系结构和功能。硬件说明语言基本上描述了输入信号与数字电路与输出信号之间的关系。这样,它可以在文本上表示任何真实表,布尔函数或布尔表达。HDL通常具有人类可读的语法,以及软件工具(设计应用程序)。
Fig. 1: Representational Image for Hardware Description Languages
使用HDL的数字集成电路的设计过程涉及以下步骤 -
1)设计条目:这是设计数字集成电路的第一步。在此步骤中,HDL用于描述数字电路的功能。该描述可以是真实表,布尔方程式,互连逻辑门或行为模型的网列的形式。大而复杂的数字电路可以分为小型功能单元或模型,然后与每个单元具有自身的功能和行为相互联系。
2)Logic Simulation:在此步骤中,基于HDL语句的数字电路将作为输入和输出信号的时间排序序列或输入和输出信号的波形中进行模拟。数字电路的仿真可用于检测电路在芯片上制造之前的逻辑设计中的任何误差。用于模拟数字电路的输入信号的逻辑值称为测试工作台。测试台也用HDL编写。通过模拟数字设计,检测到电路逻辑中的误差,然后校正各自的HDL语句以得出所需的输出信号。
3)设计合成:在此步骤中,数字电路通过编程方式合成为所需物理组件的数据库及其互连。数字电路的物理组件的互连称为NetList。该数据库可用于在硅芯片上制造电路,也可以用作印刷电路板上的布局。合成工具生成的数字数据库可用于使数字集成电路的制造自动化,因为在数据库中纳入了数字电路实现的实际过程。
4)Timing Verification: The digital circuits must output signals within a desired time limit. There is some propagation delay in the signal when it transits from one logic gate to another. Practically, this propagation delay must be minimized (like by two-level implementation of the boolean functions in the circuit). By time verification, the speed of the digital circuit is confirmed. The process involves checking each signal path and confirm that it is not compromised by the propagation delays. This is the final step before the fabrication of the digital circuit.
5)Fault Simulation: Before the circuit is produced, it is compared with the ideal circuit as initially described in the HDL. The production circuit may not exhibit the same behaviour as the ideal circuit in case there may induce some fault in the circuit. The production circuit must be verified being fault free before shipping. The fault simulation is always done before production to test the internal logic of the integrated circuit.
6)物理设计: In the process, the digital circuit is fabricated on a silicon chip or PCB inside a clean room. This is the production stage of the circuit. The circuit must be fabricated in a dust free environment. Even a single dust particle can cause fault in the functioning of the circuit.
有两个标准的硬件说明语言 - VHDL和Verilog。VHDL是VHSIC硬件说明语言的缩写,其中VHSIC代表非常高的集成电路。VHDL是国防部规定的IEEE标准HDL语言。Verilog是Cadence Design Systems的专有HDL语言。Cadence将Verilog的控制权转移到了以名称为单位的公司和大学的财团 - Open Verilog International。OVI Verilog被开发为IEEE标准的采用。与VHDL相比,Verilog易于使用和学习。
In the next tutorial, learn aboutarithmetic circuits。算术电路是任何中央处理单元(CPU)中算术逻辑单元(ALU)的一部分的基本数字电路。
Filed Under:Featured Contributions
Questions related to this article?
询问并讨论电气技术在线。comandEDAboard.comforums.
Tell Us What You Think!!
你一定是logged into post a comment.